1. Field of the Invention
This invention relates to a semiconductor memory device having a redundancy circuit, and more particularly to a dynamic random access memory (DRAM) which has a memory cell array divided into a large number of blocks and in which a plurality of blocks can be simultaneously activated.
2. Description of the Related Art
In recent years, the chip size of a DRAM has tended to increase as the integration density becomes higher. In order to reduce the chip size, it is effective to reduce not only the pattern size of a memory cell but also the occupied area of the peripheral circuit. For this purpose, in recent years, a column decoder tends to be commonly used by a plurality of blocks by use of a two-layered metal interconnection. That is, word lines formed of a first-level metal interconnection are arranged in parallel to the gate electrodes formed of polysilicon, column selection lines formed of a second-level metal interconnection are arranged in a direction perpendicular to the word line (in a direction parallel to the bit lines) and are commonly used for each block. The RC delay due to the word line is suppressed by short-circuiting the gate electrodes of polysilicon to the word line at some points and the peripheral circuit is made compact by placing a column decoder at one portion of the memory cell array.
FIG. 1 shows a pattern layout of the conventional chip in a 64-Mbit DRAM utilizing the above-described technique. A memory cell array 11 is divided into four subarrays 11A to 11D. Each of the subarrays 11A to 11D has a memory capacity of 16 Mbits and the subarrays 11A to 11D are respectively divided into 16 blocks of 1 Mbit 11A-1 to 11A-16, 11B-1 to 11B-16, 11C-1 to 11C-16, and 11D-1 to 11D-16. A first row decoder 12-1 which is commonly used by the subarrays 11A and 11C is arranged between the subarrays 11A and 11C. A second row decoder 12-2 which is commonly used by the subarrays 11B and 11D is arranged between the subarrays 11B and 11D. A column decoder 13A for the subarray 11A and a column decoder 13B for the subarray 11B are arranged between the subarrays 11A and 11B. Further, a column decoder 13C for the subarray 11C and a column decoder 13D for the subarray 11D are arranged between the subarrays 11C and 11D. A peripheral circuit 14 is formed in an area between the column decoders 13A and 13B and an area between the column decoders 13C and 13D. A column selection line CSLa is formed to extend over the blocks 11A-1 to 11A-16 of the subarray 11A (one column selection line is shown in FIG. 1 as a representative, but in general, a large number of column selection lines are formed in parallel). Likewise, column selection lines CSLb, CSLc and CSLd are formed to extend over the respective blocks 11B-1 to 11B-16, 11C-1 to 11C-16 and 11D-1 to 11D-16 of the subarrays 11B, 11C and 11D. The column selection lines CSLa to CSLd in the subarrays 11A to 11D are respectively selected by outputs of the column decoders 13A to 13D.
As is typically shown in the block 11A-1, paired bit lines BL, BL are formed to extend in the same direction as the column selection line CSL in each block. Further, word lines WL are formed to extend in a direction perpendicular to the paired bit lines BL, BL.
As shown in FIG. 2, in each of the blocks 11A-1 to 11A-16, 11B-1 to 11B-16, 11C-1 to 11C-16 and 11D-1 to 11D-16, memory cells MC, sense amplifiers SA, output controlling transistors T1, T2, column selection lines CSL, paired output lines DO, DO, word lines WL, and paired bit lines BL, BL are formed. Each of the column selection lines CSL is connected to the gates of the corresponding output controlling transistors T1, T2. An output of the sense amplifier SA on a column selected by a column selection signal output from the column decoder 13 is output via the paired output lines DO, DO.
The redundancy technique in the semiconductor memory device of the above-described pattern layout is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 4-103099 by the applicant of this application, corresponding U.S. Pat. No. 5,272,672, Jpn. Pat. Appln. KOKAI Publication No. 6-28890 by the applicant of this application, and corresponding U.S. patent application Ser. No. 08/035,196 filed on Mar. 22, 1993. The technique disclosed in the above Jpn. Pat. Appln. KOKAI Publications and the U.S. Patent Specifications is to relieve the memory device by use of one spare column selection line even when different column defects (containing bit defects) occur in the respective blocks.
FIG. 3 shows an example of the construction of the column decoder and spare column decoders which can relieve the memory device by use of one spare column selection line even when different column defects (containing bit defects) occur in the respective blocks in the semiconductor memory device shown in FIG. 1. The column decoder 13A effects the column selecting operation for all of the blocks 11A-1 to 11A-16 in the subarray 11A, the column decoder 13B effects the column selecting operation for all of the blocks 11B-1 to 11B-16 in the subarray 11B, the column decoder 13C effects the column selecting operation for all of the blocks 11C-1 to 11C-16 in the subarray 11C, and the column decoder 13D effects the column selecting operation for all of the blocks 11D-1 to 11D-16 in the subarray 11D. In FIG. 3, the subarray 11A is shown as a representative, but the other subarrays 11B, 11C and 11D are formed with the same construction.
In FIG. 3, spare column decoders 15-1 to 15-16 are provided to correspond to the blocks 11A-1 to 11A-16. The spare column decoders 15-1 to 15-16 are supplied with selection signals RSL1 to RSL16 of the respective blocks and a column address A0C to A7C. In the spare column decoders 15-1 to 15-16, addresses of defective columns of the respective blocks are previously programmed. The programming is executed by selectively applying a laser beam to and melting (which is hereinafter referred to as laser blow) corresponding fuses provided in the respective spare column decoders, for example. A spare column decoder 15-n (n is an integer of 1 to 16) selected by an input row address outputs a corresponding one of signals SCSL1 to SCSL16 which is set to the high level when an input column address coincides with previously programmed defective column address. The logical sum of the signals SCSL1 to SCSL16 is derived by an OR gate 16 which in turn outputs a spare column selection signal SCSL. Since a signal SCSLi (i is an integer of 1 to 16) output from a non-selected block is set at the low level, an output of the spare column decoder of the selected block is output as the signal SCSL. The signal SCSL is also input to the column decoder 13A, and when the signal SCSL is set to the high level, a normal column selection signal CSLj (j is an integer of 1 to 128) which is to be selected by the address is controlled to be set into the non-selected state.
Therefore, when a defective column address in a block corresponding to the input row address coincides with the input corresponding to the input row address coincides with the input column address A0C to A7C, a spare column selection line SCSL is selected instead of a normal column selection line CSL. With the above construction, defects of different column addresses in the respective blocks can be compensated for by use of one spare column selection line SCSL.
In the redundancy technique described in the above Jpn. Pat. Appln. KOKAI Publications and the U.S. Patent Specifications, since one of the blocks in each of the subarrays 11A to lid is activated as shown by the hatching in FIG. 4 in the case of 64-Mbit DRAM of 8K refresh cycle, the defects can be compensated for by the above-described technique. However, in the case of a 4K refresh cycle device, two blocks in each of the subarrays 11A to lid are simultaneously activated as shown in FIG. 5. At this time, if defects are present in different columns of the two blocks which are simultaneously activated, the above-described relieving method cannot be applied. The problem is explained in detail below.
That is, in a case where two blocks are simultaneously activated, two of the block selection signals RSL1 to RSL16 are raised to the high level in the circuit shown in FIG. 3. When the input column address A0C to A7C coincides with an address of the defective column in one of the two blocks which are simultaneously selected, a column selection signal SCSLi corresponding to the block is raised to the high level so that the potential of the spare column selection line SCSL will be raised to the high level. As a result, the column decoder 13A is controlled to set the normal column selection line CSL into the non-selected state. However, if a block corresponding to the actually input column address is the other one of the two blocks which are simultaneously activated, memory cells corresponding to the column address are the memory cells connected to the normal column selection line CSL, and therefore, data thereof cannot be read out. The problem can be solved by constructing the block selection signal to determine whether the column selection signal SCSLi is output or not by referring to not only the row address but also the column address, but in this case, the column selection signal SCSLi is set to the high level after inputting of the column address A0C to A7C and then the column selection signal SCSL is raised to the high level. As a result, a period of time from the inputting of the column address A0C to A7C to the outputting of the signals SCSL and SCL becomes longer and the access time is made longer.
FIG. 6 shows the manufacturing yield of a device when attention is paid to one subarray, that is, 16 Mbits when a 64-Mbit DRAM is formed by use of the above redundancy technique. In FIG. 6, the abscissa indicates the probability that a randomly selected column is defective and indicates the quality (maturity or the degree of completeness) of the manufacturing line. The ordinate indicates the yield for the probability of defects. A solid line 21 indicates the yield in a case where only one column in the 16 Mbits can be compensated for, that is, where the above redundancy technique is not used, solid lines 22 to 24 indicate yields in a case where the above redundancy technique is used. The solid line 22 indicates the yield in the case of 8K refresh cycle, the solid line 23 indicates the yield in the case of 4K refresh cycle, and the solid line 24 indicates the yield in the case of 2K refresh cycle. As shown in FIG. 6, the relieving efficiency can be enhanced and the manufacturing yield can be improved by use of the technique disclosed in the Jpn. Pat. Appln. KOKAI Publications and the U.S. Patent Specifications cited before.
However, if the refresh cycle is lowered and a plurality of blocks in one subarray are simultaneously activated and when addresses of different defective columns are present in the respective blocks which are simultaneously activated, the defective columns cannot be relieved. Therefore, as is clearly shown in FIG. 6, the relieving effect is lowered as the refresh cycle is lowered to a smaller value such as 4K, 2K (as the number of blocks which are simultaneously activated is increased).